COURSE UNIT TITLE

: PHASE LOCKED LOOP THEORY AND APPLICATIONS

DEGREE PROGRAMMES

Description of Individual Course Units

Course Unit Code Course Unit Title Type Of Course D U L ECTS
EEE 5083 PHASE LOCKED LOOP THEORY AND APPLICATIONS ELECTIVE 3 0 0 8

Offered By

Graduate School of Natural and Applied Sciences

Level of Course Unit

Second Cycle Programmes (Master's Degree)

Course Coordinator

ASSOCIATE PROFESSOR SELÇUK KILINÇ

Offered to

ELECTRICAL AND ELECTRONICS ENGINEERING
ELECTRICAL AND ELECTRONICS ENGINEERING
ELECTRICAL AND ELECTRONICS ENGINEERING

Course Objective

Students are able to learn that what a Phase Locked Loop circuit is and to understand a Phase Locked Loop circuit's function in an electronic system.
The main differences between Phase Locked Loop circuits namely analog, digital and software. Students are able to know analysis and application of the different PLL circuits.

Learning Outcomes of the Course Unit

1   The students are expected to learn what phaselock is and history of PLL circuits
2   The students are expected to understand the different phase detector circuits, characteristics, pros and cons in a phase locked loop circuit
3   The students are expected to learn other loop elements such that Voltage Controlled Oscillator and role of filters in a PLL circuit
4   The students are expected to analyse a Phase Locked loop circuit ( both analog and digital) in frequency domain.
5   The students are expected to understand software Phase Locked Loop systems
6   The students are expected to understand working mechanism of PLL's in different applications for example Frequency Synthesizer, Demodulation and phase shifters

Mode of Delivery

Face -to- Face

Prerequisites and Co-requisites

None

Recomended Optional Programme Components

None

Course Contents

Week Subject Description
1 Introduction/ History of Phase-Locked Loop Circuits
2 Phase-Locked Loop Fundamentals, Transfer Function of Loop elements
3 Phase Detectors; Multiplier , Sequential type and Two-Phase Phase Detectors
4 Voltage Controlled Oscillator and Loop Filters; PLL type/order
5 Tracking and Acquition of a PLL
6 Mid-Term Exam I
7 PLL Frquency Synthesizers
8 PLL Modulators and Demodulators
9 Miscellaneous Applications of Phase Lock Loops
10 Anamalous Locking
11 Digital Phase-Locked Loops
12 Software PLL 1
13 Jitter and Noise reduction in PLL circuits 1
14 Mid-Term Exam II 1

Recomended or Required Reading


1) F.M.Gardner, Phaselock Techniques, third edition, John Wiley, New York, 2005, ( ISBN:0-471-43063-3)

2) J.W.M, Rogers, C. Plett, Radio Frequency Integrated Circuit Design, second edition, Artech House, Norwood, 2010, ( ISBN-13: 978-1-60783-979-8)

3) R.E. Best, Phase-Locked Loops: Theory, Design and Applications, Fourth edition, Mc-Graw Hill,1999.

Planned Learning Activities and Teaching Methods

1. Lectures,
2. Homework,
3. Practical assigments,
4. Lab Demos,

Assessment Methods

SORTING NUMBER SHORT CODE LONG CODE FORMULA
1 PRJ PROJECT
2 MTE MIDTERM EXAM
3 FIN FINAL EXAM
4 FCG FINAL COURSE GRADE PRJ * 0.30 + MTE * 0.30 + FIN * 0.40
5 RST RESIT
6 FCGR FINAL COURSE GRADE (RESIT) PRJ * 0.30 + MTE * 0.30 + RST * 0.40


*** Resit Exam is Not Administered in Institutions Where Resit is not Applicable.

Further Notes About Assessment Methods

Exams,
Practical assignment ( PLL circuit Design for given function)

Assessment Criteria

1) Mid-term Exam I Worth 15%
2) Mid-term Exam II Worth 15%
3) Final Exam worth 50%
4) Final Project worth 20%

Language of Instruction

English

Course Policies and Rules

Contact Details for the Instructor: haldun.karacadeu.edu.tr

Contact Details for the Lecturer(s)

Prof.Dr. Haldun Karaca
Dokuz Eylül Üniversitesi, Mühendislik Fakültesi
Elektrik ve Elektronik Mühendisliği Bölümü
Tınaztepe Kampusu, 35160 Buca Izmir

Office Hours

Mon. 09.00 - 12.00, others by appointment.

Work Placement(s)

None

Workload Calculation

Activities Number Time (hours) Total Work Load (hours)
Lectures 13 3 39
Preparations before/after weekly lectures 13 4 52
Design Project 1 50 50
Preparation for midterm exam 1 20 20
Preparation for final exam 1 30 30
Preparation for quiz etc. 0 0 0
Preparing presentations 0 0 0
Preparing assignments 0 0 0
Final 1 3 3
Midterm 1 3 3
Quiz etc. 0 0 0
TOTAL WORKLOAD (hours) 197

Contribution of Learning Outcomes to Programme Outcomes

PO/LOPO.1PO.2PO.3PO.4PO.5PO.6PO.7PO.8PO.9PO.10PO.11PO.12PO.13PO.14PO.15
LO.153
LO.253
LO.3523
LO.45243
LO.5523
LO.65243

CONTACT INFORMATION
Dokuz Eylül Üniversitesi Cumhuriyet Bulvarı No: 144 35210 Alsancak / İZMİR
Phone: +90(232) 412 12 12 - Fax: +90 (232) 464 81 35

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