COURSE UNIT TITLE

: ADVANCED COMPUTER ARCHITECTURE

Description of Individual Course Units

Course Unit Code Course Unit Title Type Of Course D U L ECTS
CSE 6004 ADVANCED COMPUTER ARCHITECTURE ELECTIVE 3 0 0 8

Offered By

Graduate School of Natural and Applied Sciences

Level of Course Unit

Second Cycle Programmes (Master's Degree)

Course Coordinator

PROFESSOR DOCTOR RECEP ALP KUT

Offered to

Computer Engineering (English)
Computer Engineering (English)
COMPUTER ENGINEERING (ENGLISH)

Course Objective

The main aim of this course is to introduce computer processors, memory organization and brief view about the relationship between CPU and its peripherals.It is expected that students at the end of this course will be able to design a stored program computer using logic gates, flip-flops, and components from a given library of digital components.

Learning Outcomes of the Course Unit

1   Understand the main concepts of computer architecture
2   Design and analyze the main functional units of a computer
3   Mention some of the strategies used in CISC and RISC architectures
4   Implement assembly programs that accomplish basic computational and I/O operations by using assambly of Basic Computer
5   Define some concepts of memory organization: main memory, cache memory and virtual memory
6   Illustrate the principles basic characteristics of multiprocessors, pipelining, vector processing, cache coherence
7   Provide knowledge about interfacing; I/O fundamentals such as handshaking, and I/O techniques such interrupt driven I/O and DMA

Mode of Delivery

Face -to- Face

Prerequisites and Co-requisites

None

Recomended Optional Programme Components

None

Course Contents

Week Subject Description
1 Introduction, Combinatorial and Sequential Circuit review
2 Basic Computer Org. and Design: Registers Transfers and Microoperations
3 Basic Computer Org. and Design: Memory Reference Inst., Basic CPU Design
4 Programming the Basic Computer, Introduction to Assembly Language
5 Microprogrammed Control
6 Computer Arithmetic
7 Central Processing Unit: Stacks, Instruction Format, Addressing Modes
8 Central Processing Unit: Data Transfer Instructions, Program Control, RISC
9 Pipeline and Vector Processing
10 Input-Output Org.: Interfaces, Asynch. Data Transfer, Priority Interrupt, DMA
11 Input-Output Organization: I/O Processor, Serial Communication,
12 Memory Organization: Main Memory, Cache Memory
13 Memory Organization: Virtual Memory, Memory Management Hardware
14 Multiprocessors

Recomended or Required Reading

Computer System Architecture,Mano Morris,Prentice Hall,1993
Mano M. M., Kime C.R., (2001), "Logic and Computer Design Fundamentals", 2nd Edition, Prentice Hall.
Hennessy J. L., Patterson D. A., (2003), "Computer Organization and Design: A Quantative Approach", 3rd Edition, Morgan Kaufmann
Stallings W., (2006), "Computer Organization & Architecture: Designing for Performance", 7th Edition, Prentice Hall

Planned Learning Activities and Teaching Methods

Lectures
Literature Research
Presentation
Term Project

Assessment Methods

SORTING NUMBER SHORT CODE LONG CODE FORMULA
1 ASG ASSIGNMENT
2 PRS PRESENTATION
3 FCG FINAL COURSE GRADE ASG * 0.50 + PRS * 0.50


*** Resit Exam is Not Administered in Institutions Where Resit is not Applicable.

Further Notes About Assessment Methods

None

Assessment Criteria

Assessment will be the success level of presentation and the final report of term project.

Language of Instruction

English

Course Policies and Rules

To be announced.

Contact Details for the Lecturer(s)

Dokuz Eylul University
Department of Computer Engineering
Tinaztepe Campus Buca - IZMIR

Tel: +90 (232) 3017401

Office Hours

Thursday 9:30 - 10:30

Work Placement(s)

None

Workload Calculation

Activities Number Time (hours) Total Work Load (hours)
Lectures 14 3 42
Preparations before/after weekly lectures 14 2 28
Preparing assignments 1 42 42
Preparing presentations 2 25 50
Reading 1 26 26
TOTAL WORKLOAD (hours) 188

Contribution of Learning Outcomes to Programme Outcomes

PO/LOPO.1PO.2PO.3PO.4PO.5PO.6PO.7PO.8PO.9PO.10PO.11
LO.142233323
LO.25445345335
LO.352233323
LO.4544533434
LO.5533543444
LO.652335323
LO.753333