COURSE UNIT TITLE

: COMPUTER ARCHITECTURE

DEGREE PROGRAMMES

Description of Individual Course Units

Course Unit Code Course Unit Title Type Of Course D U L ECTS
CME 2206 COMPUTER ARCHITECTURE COMPULSORY 3 2 0 6

Offered By

Computer Engineering

Level of Course Unit

First Cycle Programmes (Bachelor's Degree)

Course Coordinator

ŞERIFE YILMAZ

Offered to

Computer Engineering

Course Objective

The main aim of this course is to introduce computer processors, memory organization nd brief view about the relationship between CPU and its peripherals.It is expected that students at the end of this course will be able to design a stored program computer using logic gates, flip-flops, and components from a given library of digital components.

Learning Outcomes of the Course Unit

1   Understand the main concepts of computer architecture
2   Design and analyze the main functional units of a computer
3   Mention some of the strategies used in CISC and RISC architectures
4   Implement assembly programs that accomplish basic computational and I/O operations by using assambly of Basic Computer
5   Define some concepts of memory organization: main memory, cache memory and virtual memory
6   Illustrate the principles basic characteristics of multiprocessors, pipelining, vector processing, cache coherence
7   Provide knowledge about interfacing; I/O fundamentals such as handshaking, and I/O techniques such interrupt driven I/O and DMA

Mode of Delivery

Face -to- Face

Prerequisites and Co-requisites

None

Recomended Optional Programme Components

None

Course Contents

Week Subject Description
1 Introduction, Combinatorial and Sequential Circuit review
2 Basic Computer Org. and Design: Registers Transfers and Microoperations,
3 Basic Computer Org. and Design: Memory Reference Inst., Basic CPU Design
4 Programming the Basic Computer, Introduction to Assembly Language
5 Microprogrammed Control, Computer Arithmetic
6 Central Processing Unit: Stacks, Instruction Format, Addressing Modes
7 Review for Midterm and Solve Questions
8 Central Processing Unit: Data Transfer Instructions, Program Control, RISC
9 Pipeline and Vector Processing
10 Input-Output Org.: Interfaces, Asynch. Data Transfer, Priority Interrupt, DMA
11 Input-Output Organization: I/O Processor, Serial Communication
12 Memory Organization: Main Memory, Cache Memory
13 Memory Organization: Virtual Memory, Memory Management Hardware
14 Multiprocessors

Recomended or Required Reading

Computer System Architecture,Mano Morris,Prentice Hall,1993
Mano M. M., Kime C.R., (2001), "Logic and Computer Design Fundamentals", 2nd Edition,
Prentice Hall.
Hennessy J. L., Patterson D. A., (2003), "Computer Organization and Design: A
Quantative Approach", 3rd Edition, Morgan Kaufmann
Stallings W., (2006), "Computer Organization & Architecture: Designing for
Performance", 7th Edition, Prentice Hall

Planned Learning Activities and Teaching Methods

Presentation/Lecturing, Interactive discussion, Application, Homework, Laboratory

Assessment Methods

SORTING NUMBER SHORT CODE LONG CODE FORMULA
1 MTE MIDTERM EXAM
2 ASG ASSIGNMENT
3 LAB LABORATORY
4 FIN FINAL EXAM
5 FCG FINAL COURSE GRADE MTE * 0.25 + ASG * 0.10 + LAB * 0.15 + FIN * 0.50
6 RST RESIT
7 FCGR FINAL COURSE GRADE (RESIT) MTE * 0.25 + ASG * 0.10 + LAB * 0.15 + RST * 0.50


Further Notes About Assessment Methods

None

Assessment Criteria

Midterm, Final, Homework, LAB

Language of Instruction

English

Course Policies and Rules

Participation is mandatory.

Contact Details for the Lecturer(s)

Şerife SUNGUN
Dokuz Eylül Üniversitesi
Mühendislik Fakültesi
Bilgisayar Mühendisliği Bölümü
Tınaztepe Kampüsü
Buca/Izmir/ TURKEY

Office Hours

Monday 10:30 - 12:00

Work Placement(s)

None

Workload Calculation

Activities Number Time (hours) Total Work Load (hours)
Tutorials 14 2 28
Lectures 14 3 42
Preparations before/after weekly lectures 14 3 42
Preparing assignments 5 3 15
Preparation for final exam 1 10 10
Preparation for midterm exam 1 9 9
Midterm 1 2 2
Final 1 2 2
TOTAL WORKLOAD (hours) 150

Contribution of Learning Outcomes to Programme Outcomes

PO/LOPO.1PO.2PO.3PO.4PO.5PO.6PO.7PO.8PO.9PO.10
LO.14233
LO.25455435
LO.352333
LO.45455343
LO.553543
LO.652333
LO.75333

CONTACT INFORMATION
Dokuz Eylül Üniversitesi Cumhuriyet Bulvarı No: 144 35210 Alsancak / İZMİR
Phone: +90(232) 412 12 12 - Fax: +90 (232) 464 81 35

Copyright 2015 DEÜ. BİD

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