COURSE UNIT TITLE

: ADVANCED LOGIC DESIGN

DEGREE PROGRAMMES

Description of Individual Course Units

Course Unit Code Course Unit Title Type Of Course D U L ECTS
EED 4521 ADVANCED LOGIC DESIGN ELECTIVE 4 0 0 6

Offered By

Electrical and Electronics Engineering (English)

Level of Course Unit

First Cycle Programmes (Bachelor's Degree)

Course Coordinator

PROFESSOR DOCTOR UĞUR ÇAM

Offered to

Electrical and Electronics Engineering (English)

Course Objective

The aim of the course is to present advanced logic design and implementation techniques. Verilog Hardware description Language will be introduced. Advanced logic optimization and simulation techniques will be presented. Digital system design using Programmable Logic Devices (PLD) and Field Programmable Gate Arrays (FPGA) will be examined.

Learning Outcomes of the Course Unit

1   To be able to design synchronous and asynchronous digital circuits using SystemVerilog hardware description language.
2   To be able to simulate and synthesize advanced digital circuit designs using Electronic Design Automation (EDA) tools.
3   To be able to implement advanced digital circuit designs on PLD and FPGA devices.
4   To be able to optimize logic circuits.
5   To be able to test logic circuits.

Mode of Delivery

Face -to- Face

Prerequisites and Co-requisites

EED 3018 - MICROPROCESSOR SYSTEMS

Recomended Optional Programme Components

None

Course Contents

Week Subject Description
1 Course Outline, Review of logical design methods, Implementation Technologies.
2 Optimized implementation of logic functions.
3 SystemVerilog data types and operators, Verilog ile gate level and RTL modelling of logic circuits.
4 SystemVerilog Behavioral models, number representations and aricmetic circuits, aricmetic operations.
5 SystemVerilog specifications of combinational logic circuits.
6 SystemVerilog specifications of combinational logic building blocks.
7 SystemVerilog specifications of sequential logic circuits.
8 SystemVerilog specifications of sequential logic circuits.
9 Mealy & Moore machines, finite state machine design, state minimization.
10 SystemVerilog representation of finite state machines.
11 SystemVerilog representation of algorithmic state machines.
12 Switch level digital circuit design with SystemVerilog.
13 Testing of logic circuits. Hazards in digital circuits.
14 Digital system design using Programmable Logic Devices (PLD) and Field Programmable Gate Arrays (FPGA).

Recomended or Required Reading

Textbook(s):
1) Digital Design and Computer Architecture: RISC-V Edition, Sarah L. Harris and David Harris , Morgan Kaufmann (Elsevier), 2022.
2) CMOS VLSI Design, 4th Edition, Neil Weste and David Harris, Pearson Education, 2010.
3) Digital System Design with SystemVerilog, Mark Zwolinski, Prentice Hall, 2009.
4) Logic & Computer Design Fundamentals, 5th Edition, M. Morris R. Mano, Charles R. Kime and Tom Martin, Pearson Education, 2016.

Supplementary Book(s):
1) Digital Fundamentals, 11th Edition, Thomas Floyd , Pearson, 2014.
2) Digital Design, First Edition, Frank Vahid, John Wiley and Sons Publishers, 2007.
3) Digital System Designs and Practices: Using Verilog HDL and FPGAs, First Edition, Ming-Bo Lin, John Wiley & Sons, 2008.

Planned Learning Activities and Teaching Methods

Lectures, homework.

Assessment Methods

SORTING NUMBER SHORT CODE LONG CODE FORMULA
1 MTE MIDTERM EXAM
2 ASG ASSIGNMENT
3 FIN FINAL EXAM
4 FCG FINAL COURSE GRADE MTE * 0.25 + ASG * 0.25 + FIN * 0.50
5 RST RESIT
6 FCGR FINAL COURSE GRADE (RESIT) MTE * 0.25 + ASG * 0.25 + RST * 0.50


Further Notes About Assessment Methods

None

Assessment Criteria

1,2,3,4,5 numbered course outcomes are evaluated by exams and assignments.

Language of Instruction

English

Course Policies and Rules

To be announced.

Contact Details for the Lecturer(s)

Prof. Dr. Uğur Çam
Dokuz Eylül University
Engineering Faculty
Electrical-Electronics Engineering
e-mail:ugur.cam@deu.edu.tr

Office Hours

-

Work Placement(s)

None

Workload Calculation

Activities Number Time (hours) Total Work Load (hours)
Lectures 14 4 56
Preparations before/after weekly lectures 14 3 42
Preparation for midterm exam 1 10 10
Preparation for final exam 1 10 10
Preparing assignments 5 6 30
Midterm 1 2 2
Final 1 2 2
TOTAL WORKLOAD (hours) 152

Contribution of Learning Outcomes to Programme Outcomes

PO/LOPO.1PO.2PO.3PO.4PO.5PO.6PO.7PO.8PO.9PO.10PO.11PO.12PO.13
LO.155535223
LO.255535223
LO.355535223
LO.455535223
LO.555535223

CONTACT INFORMATION
Dokuz Eylül Üniversitesi Cumhuriyet Bulvarı No: 144 35210 Alsancak / İZMİR
Phone: +90(232) 412 12 12 - Fax: +90 (232) 464 81 35

Copyright 2015 DEÜ. BİD

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