COURSE UNIT TITLE

: DIGITAL ELECTRONICS

Description of Individual Course Units

Course Unit Code Course Unit Title Type Of Course D U L ECTS
EED 3003 DIGITAL ELECTRONICS COMPULSORY 3 2 0 6

Offered By

Electrical and Electronics Engineering

Level of Course Unit

First Cycle Programmes (Bachelor's Degree)

Course Coordinator

PROFESSOR UĞUR ÇAM

Offered to

Electrical and Electronics Engineering

Course Objective

This course covers basic principles digital electronics circuits. After detailed investigation of ADC and DAC circuits, PLL circuits will be given. Design and analysis both CMOS and TTL digital electronics circuits is als covered. At the end memory circuits will explained.

Learning Outcomes of the Course Unit

1   ADC and DAC circuits
2   PLL circuits
3   CMOS digital circuits
4   TTL digital circuits
5   Memory circuits

Mode of Delivery

Face -to- Face

Prerequisites and Co-requisites

EED 2003 - LOGIC DESIGN

Recomended Optional Programme Components

None

Course Contents

Week Subject Description
1 Introduction
2 ADC and DAC specifications
3 ADC circuits
4 DAC circuits
5 Phase locked loop circuits
6 Phase locked loop circuits
7 CMOS digital circuits
8 Midterm
9 BJT digital circuits
10 TTL digital circuits
11 Memory circuits
12 Programmable circuits
13 Timing circuits
14 Summary and Discussion

Recomended or Required Reading

Textbook: A. Sedra and K. Smith:Microelectronic Devices, Oxford University Pres.
Additional Book:K. Eshraghian, N. Weste: CMOS VLSI design, Addison-Wesley Publishing, Third Edition, 2004

Planned Learning Activities and Teaching Methods

Lecture+Labaratory+Exam

Assessment Methods

SORTING NUMBER SHORT CODE LONG CODE FORMULA
1 MTE MIDTERM EXAM
2 LAB LABORATORY
3 FIN FINAL EXAM
4 FCG FINAL COURSE GRADE MTE * 0.30 + LAB * 0.20 + FIN * 0.50
5 RST RESIT
6 FCG FINAL COURSE GRADE MTE * 0.30 + LAB * 0.20 + RST * 0.50


*** Resit Exam is Not Administered in Institutions Where Resit is not Applicable.

Further Notes About Assessment Methods

None

Assessment Criteria

1,2,3,4,5 numbered course outcomes is evaluated by laboratory works, midterm and final exams.

Language of Instruction

English

Course Policies and Rules

%70 attendance for lectures and %80 attendance for labs are mandatory.

Contact Details for the Lecturer(s)


Prof. Dr. Ugur Cam
Dokuz Eylül University
Engineering Faculty
Electrical and Electronics Engineering
Tinaztepe, Buca, 35160, Izmir, Turkey
Phone: +90 232 3017197
Fax : +90 232 4534279
e-mail: ugur.cam@eee.deu.edu.tr
e-mail: ugur_cam@yahoo.com
http://www.eee.deu.edu.tr/~ucam

Office Hours

To be announced.

Work Placement(s)

None

Workload Calculation

Activities Number Time (hours) Total Work Load (hours)
Lectures 14 3 42
Laboratory 14 2 28
Preparation for midterm exam 1 10 10
Preparation for final exam 1 10 10
Preparations before/after weekly laboratory (6 laboratory works) 6 5 30
Preparations before/after weekly lectures 14 1 14
Midterm 1 2 2
Final 1 2 2
TOTAL WORKLOAD (hours) 138

Contribution of Learning Outcomes to Programme Outcomes

PO/LOPO.1PO.2PO.3PO.4PO.5PO.6PO.7PO.8PO.9PO.10PO.11PO.12PO.13
LO.15
LO.255
LO.35
LO.455
LO.5555