COURSE UNIT TITLE

: LOGIC DESIGN

Description of Individual Course Units

Course Unit Code Course Unit Title Type Of Course D U L ECTS
EED 2003 LOGIC DESIGN COMPULSORY 3 2 0 6

Offered By

Electrical and Electronics Engineering

Level of Course Unit

First Cycle Programmes (Bachelor's Degree)

Course Coordinator

ASISTANT PROFESSOR AHMET ÖZKURT

Offered to

Electrical and Electronics Engineering

Course Objective

Aim of the lesson is to teach computer design fundamentals which requires number systems, boolean algebra, Combinational and Sequential digital circuits, components and high level integrated circuits to the students.

Learning Outcomes of the Course Unit

1   To remember number systems and conversions
2   to give boolean algebric operations
3   to inform combinational and Sequential circuit Fundamentals
4   to understand circuit minimization and needs for the application
5   To inform logic Gates, flip flops and SSI-MSI integrated circuits
6   To understand analysis and degin procedure of logic circuits.
7   To inform hardware implementation and specifications of logic Gates
8   To inform to design complex digital systems

Mode of Delivery

Face -to- Face

Prerequisites and Co-requisites

None

Recomended Optional Programme Components

None

Course Contents

Week Subject Description
1 Number Systems, Binary systems
2 Boolean algebra, Boolean Theorems
3 Boolean function simplification
4 logic Gates
5 introduction to HDL and verilog
6 Map simplification method, Circuit implementation
7 Combinational logic Design and analysis procedure
8 midterm
9 Decoders, , multiplexers, encoders, ROMs and circuit implementations, HDL syntax
10 latches, Flipflops
11 Sequential synchronous logic Design and analysis Procedure
12 Registers, counters, RAMs
13 HDL and verilog applications of logic circuits simulations
14 Overview

Recomended or Required Reading

Main Reference: Digital Design, M.Morris Mano, Prentice Hall , ISBN 0130621218, 2002
Sub-Reference: Digital Design, John. F. Wakerly, Prentice Hall , ISBN 0130898961, 2001

Planned Learning Activities and Teaching Methods

In this lesson, fundamental knowledge of the students will be improved by the given literature and with laboratory experiments, some practical implementations will be realized.

Assessment Methods

SORTING NUMBER SHORT CODE LONG CODE FORMULA
1 MTE MIDTERM EXAM
2 QUZ QUIZ
3 TP TERM PAPER
4 FIN FINAL EXAM
5 FCG FINAL COURSE GRADE MTE*0.25 + QUZ *0.05 + TP *0.20 + FIN * 0.50
6 RST RESIT
7 FCGR FINAL COURSE GRADE (RESIT) MTE *0.25 + QUZ *0.05 + ASG *0.20 + RST * 0.50


*** Resit Exam is Not Administered in Institutions Where Resit is not Applicable.

Further Notes About Assessment Methods

None

Assessment Criteria

In the midterm and final exams,1. to remember number systems and conversions 2.to give boolean algebric operations 3. to inform combinational and Sequential circuit Fundamentals 4. to understand circuit minimization and needs for the application. 5. To inform logic Gates, flip flops and SSI-MSI integrated circuits ,6.To understand analysis and degin procedure of logic circuits.
In the laboratories,1. to remember number systems and conversions 2.to give boolean algebric operations 3.to inform combinational and Sequential circuit Fundamentals, 4. to understand circuit minimization and needs for the application. 5.To inform logic Gates, flip flops and SSI-MSI integrated circuits, 6. To understand analysis and degin procedure of logic circuits. 7.To inform hardware implementation and specifications of logic Gates, 8To inform to design complex digital systems
will be tested.

Language of Instruction

English

Course Policies and Rules

To be announced.

Contact Details for the Lecturer(s)

Yard.doç.Dr. Ahmet ÖZKURT
E-Mail: ahmet.ozkurt@ deu.edu.tr Tel: 0232 3017134
Yard.doç.Dr. Hakkı Tarkan YALAZAN
E-Mail: hakki.yalazan@ deu.edu.tr Tel: 0232 3017134

Office Hours

2 hours per week

Work Placement(s)

None

Workload Calculation

Activities Number Time (hours) Total Work Load (hours)
Lectures 13 3 39
Tutorials 14 2 28
Preparations before/after weekly lectures 14 3 42
Preparation for midterm exam 1 10 10
Preparation for final exam 1 10 10
Preparing the laboratory notebook 14 2 28
Final 1 2 2
Midterm 1 2 2
TOTAL WORKLOAD (hours) 161

Contribution of Learning Outcomes to Programme Outcomes

PO/LOPO.1PO.2PO.3PO.4PO.5PO.6PO.7PO.8PO.9PO.10PO.11PO.12PO.13
LO.1421
LO.232
LO.3142
LO.442223343
LO.5142
LO.64442
LO.7313
LO.82213423